CPUinfo is a compact library written in the x86 assembly language completely. It comprises a set of functions to identify various 32-bit and 64-bit x86 processors ranging from those released in 1980's like 386DX to the latest ones of the Intel Core and AMD Phenom microarchitectures. The primary routine called cpuinfo_main() analyses vendor\family\model\stepping data reported by CPUID and looks up at the built in table to identify a processor properly as well as technological process used to manufacture it. There is also a veryaccurate clock speed evaluating mechanism which works even for many of those old processors not supporting TSC (Time-Stamp Counter).
 
The second part of the primary routine analyses processor cache and TLB descriptors. They are implemented in all Intel processors starting with the Coppermine family of Pentium III and in all AMD processors starting with the K6 family. VIA and Cyrix processors are also honoured.
 
There are several functions to detect and report (a bit mask is returned) various processor features which are gathered into sets such as:
 

scalar instructions	cpuinfo_scalar_ext()
vector instructions	cpuinfo_vector_ext()
general purpose instructions	cpuinfo_general_ext()
addressing extensions	cpuinfo_address_ext()
monitoring extensions	cpuinfo_monitor_ext()
other extensions	cpuinfo_other_ext()
Hyper-Threading support	cpuinfo_htt_check()

In general, every routine of the above can operate in either verbose or silent mode. Both of them return bit masks of processor features detected by a particular function, but those features are also displayed when in verbose mode. Although keep in mind that cpuinfo_main() can report only a small fraction of information through its bit mask.
 
All functions are well documented in the source code, no need to reproduce it here. For developers' convenience, there is an example wrapper available which is written in the ANSI C language.
 
CPUinfo is available for DOS & Windows as well as various UNIX-like operating systems such as Linux, FreeBSD, NetBSD and OpenBSD. Both DOS and UNIX releases are related very much and kept synchronised. The best thing is that the software is distributed for free with the complete source code under the terms of The Alasir Licence (TAL), a liberal fairly one. By the way, there is no better or just comparable open-source alternative to CPUinfo probably, so go ahead and pick up the distribution of your choice. The current release is of the 1st of December 2007.
 
CPUinfo (UNIX) — the source code (23Kb).
 
CPUinfo (DOS) — the source code and a pre-compiled optimised executable (56Kb).
 
See below for a few actual CPUinfo outputs.
 

GenuineIntel family 6 model F stepping 7
Intel Core 2 Quad (Kentsfield) 65nm processor 2667.133MHz
BIOS name string: "Intel(R) Core(TM)2 Quad CPU           @ 2.66GHz"
(4x) I-cache: 32Kb, 8-way, 64 bytes per line
(4x) D-cache: 32Kb, 8-way, 64 bytes per line
(4x) I-TLB (4Kb pages): 128 entries, 4-way
(4x) I-TLB (4Mb pages): 4 entries, 4-way
(4x) D-TLB (4Kb pages): 256 entries, 4-way
(4x) D-TLB (4Mb pages): 32 entries, 4-way
(2x) S-cache: 4096Kb, 16-way, 64 bytes per line
Scalar: FPU CMOV CX8 CX16 AMD64
Vector: MMX MMX+ SSE SSE2 SSE3
General: MSR FXSR CLFSH SENTER VMX
Addressing: PSE PSE36 PAE PGE PAT MTRR
Monitoring: TSC TMSC TM TM2
Other: VME DE MCE MCA APIC DS SS NX DCA

AuthenticAMD family F model 5 stepping 8
AMD Athlon 64 FX (Sledgehammer) 130nm processor 2420.175MHz
BIOS name string: "AMD Athlon(tm) 64 FX-51 Processor"
I-cache: 64Kb, 2-way, 1 line(s) per tag, 64 bytes per line
D-cache: 64Kb, 2-way, 1 line(s) per tag, 64 bytes per line
I-TLB (4Kb pages): 32 entries, 32-way
I-TLB (4Mb pages): 4 entries, 4-way
D-TLB (4Kb pages): 32 entries, 32-way
D-TLB (4Mb pages): 4 entries, 4-way
S-cache: 1024Kb, 16-way, 1 line(s) per tag, 64 bytes per line
S-TLB (4Kb pages): 512 entries, 4-way
Scalar: FPU CMOV CX8 AMD64
Vector: MMX MMX+ 3DNow! 3DNow!+ SSE SSE2
General: MSR FXSR CLFSH SENTER SCALL
Addressing: PSE PSE36 PAE PGE PAT MTRR
Monitoring: TSC
Other: VME DE MCE MCA APIC NX

GenuineIntel family F model 2 stepping 9
Intel Pentium 4 (Northwood) 130nm processor 2998.133MHz
BIOS name string: "Intel(R) Pentium(R) 4 CPU 2.66GHz"
I-cache: 12Kuops, 8-way
D-cache: 8Kb, 4-way, 64 bytes per line
I-TLB (4Kb pages): 128 entries, 128-way
I-TLB (4Mb pages): 128 entries, 128-way
D-TLB (4Kb pages): 64 entries, 64-way
D-TLB (4Mb pages): 64 entries, 64-way
S-cache: 512Kb, 8-way, 64 bytes per line
Scalar: FPU CMOV CX8
Vector: MMX MMX+ SSE SSE2
General: MSR FXSR CLFSH SENTER
Addressing: PSE PSE36 PAE PGE PAT MTRR
Monitoring: TSC TMSC TM
Other: VME DE MCE MCA APIC DS SS
HTT: 1 logical core(s) supported

AuthenticAMD family 6 model 4 stepping 4
AMD Athlon (Thunderbird) 180nm processor 1449.691MHz
BIOS name string: "AMD Athlon(TM)"
I-cache: 64Kb, 2-way, 1 line(s) per tag, 64 bytes per line
D-cache: 64Kb, 2-way, 1 line(s) per tag, 64 bytes per line
I-TLB (4Kb pages): 16 entries, 16-way
I-TLB (4Mb pages): 4 entries, 4-way
D-TLB (4Kb pages): 24 entries, 24-way
D-TLB (4Mb pages): 4 entries, 4-way
S-cache: 256Kb, 16-way, 1 line(s) per tag, 64 bytes per line
S-TLB (4Kb pages): 256 entries, 4-way
Scalar: FPU CMOV CX8
Vector: MMX MMX+ 3DNow! 3DNow!+
General: MSR FXSR SENTER SCALL
Addressing: PSE PSE36 PAE PGE PAT MTRR
Monitoring: TSC
Other: VME DE MCE MCA APIC

GenuineIntel family 6 model 3 stepping 4
Intel Pentium II (Klamath) 280nm processor 298.77MHz
I-cache: 16Kb, 4-way, 32 bytes per line
D-cache: 16Kb, 4-way, 32 bytes per line
I-TLB (4Kb pages): 32 entries, 4-way
I-TLB (4Mb pages): 2 entries, 2-way
D-TLB (4Kb pages): 64 entries, 4-way
D-TLB (4Mb pages): 8 entries, 4-way
S-cache: 512Kb, 4-way, 32 bytes per line
Scalar: FPU CMOV CX8
Vector: MMX
General: MSR SENTER
Addressing: PSE PAE PGE MTRR
Monitoring: TSC
Other: VME DE MCE MCA

CyrixInstead family 6 model 0 stepping 0
Cyrix model 52 stepping 0 revision 8
Cyrix 6x86MX (M2) 0.35u-0.18u processor 279.842MHz
U-cache: 64Kb, 4-way, 32 bytes per line
U-TLB (4Kb pages): 16 entries, 1-way
S-TLB (4Kb pages): 384 entries, 6-way
Scalar: FPU CMOV CX8
Vector: MMX
General: MSR
Addressing: PGE
Monitoring: TSC
Other: DE