1. Introduction.
2. Arithmetical and logical instructions.
3. Comparing and shifting instructions.
4. Converting instructions.
5. Transferring and state managing instructions.
 

 
PCMPEQ (Packed CoMPare for EQual):
 
PCMPEQB [0x0F74]
PCMPEQW [0x0F75]
PCMPEQD [0x0F76]
 
src: mm, mem64
dst: mm
 
Compare data elements in the destination operand to data elements in the source operand. If corresponding data elements of both operands are equal, the data element in the destination operand is set to all ones. Otherwise, it's set to all zeros. Packed byte (PCMPEQB), packed word (PCMPEQW), and packed doubleword (PCMPEQD) data types are recognised.
 
 
PCMPGT (Packed CoMPare for Greater Than):
 
PCMPGTB [0x0F64]
PCMPGTW [0x0F65]
PCMPGTD [0x0F66]
 
src: mm, mem64
dst: mm
 
Compare signed data elements in the destination operand to signed data elements in the source operand. If a data element in the destination operand is greater than a corresponding element in the source operand, the data element in the destination operand is set to all ones. Otherwise, it's set to all zeros. Packed byte (PCMPGTB), packed word (PCMPGTW), and packed doubleword (PCMPGTD) data types are recognised.

 
PSLL (Packed Shift Left Logical):
 
PSLLW [0x0F71/6 when using an immediate value, 0x0FF1 when not]
PSLLD [0x0F72/6 when using an immediate value, 0x0FF2 when not]
PSLLQ [0x0F73/6 when using an immediate value, 0x0FF3 when not]
 
src: mm, imm8
dst: mm
 
Shift bits of every destination data element to the left by a number of times specified in the source operand. For every destination element, freed low order bits are set to zeros. If the value specified by the source operand is greater than 15 (for words) or 31 (for doublewords) or 63 (for quadwords), then every destination element is set to all zeros. Packed word (PSLLW), packed doubleword (PSLLD), and quadword (PSLLQ) data types are recognised.
 
 
PSRL (Packed Shift Right Logical):
 
PSRLW [0x0F71/2 when using an immediate value, 0x0FD1 when not]
PSRLD [0x0F72/2 when using an immediate value, 0x0FD2 when not]
PSRLQ [0x0F73/2 when using an immediate value, 0x0FD3 when not]
 
src: mm, imm8
dst: mm
 
Shift bits of every destination data element to the right by a number of times specified in the source operand. For every destination element, freed high order bits are set to zeros. If the value specified by the source operand is greater than 15 (for words) or 31 (for doublewords) or 63 (for quadwords), then every destination element is set to all zeros. Packed word (PSRLW), packed doubleword (PSRLD), and quadword (PSRLQ) data types are recognised.
 
 
PSRA (Packed Shift Right Arithmetic):
 
PSRAW [0x0F71/4 when using an immediate value, 0x0FE1 when not]
PSRAD [0x0F72/4 when using an immediate value, 0x0FE2 when not]
 
src: mm, imm8
dst: mm
 
Shift bits of every destination data element to the right by a number of times specified in the source operand. For every destination element, freed high order bits are set to an initial value of the sign bit. If the value specified by the source operand is greater than 15 (for words) or 31 (for doublewords), then every bit of all destination elements is set to the initial value of the sign bit. Packed word (PSRAW) and packed doubleword (PSRAD) data types are recognised.